VHDL Code For Full Adder Using Components

The code for full adder using structural modelling is given below along with the source codes for various components used in the code for the full adder.

--Code for xor gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor1 is
    Port ( a : in  bit;
           b : in  bit;
           c : out  bit);
end xor1;
architecture Behavioral of xor1 is
begin
c <= a xor b;
end Behavioral; 
---------------------------------------------------------------------------------------------------------------------------
--Code for and gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and1 is
    Port ( a : in  bit;
           b : in  bit;
           c : out  bit);
end and1;
architecture Behavioral of and1 is
begin
c<= a and b;
end Behavioral;
---------------------------------------------------------------------------------------------------------------------------
--Code for or gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or1 is
    Port ( a : in  bit;
           b : in  bit;
           c : out  bit);
end or1;
architecture Behavioral of or1 is
begin
c<= a or b;
end Behavioral;
---------------------------------------------------------------------------------------------------------------------------
Code for full adder using the above components.

• SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladd is
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end fulladd;

architecture Structural of fulladd is

component or1 is
Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component xor1 is

Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component and1 is

Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

signal s1, s2, s3:STD_LOGIC;

begin

g1:xor1 port map(x,y,s1);

g2:xor1 port map(s1, cin, sum);
g3:and1 port map(x, y, s2);
g4:and1 port map(s1, cin, s3);
g5:or1 port map(s2, s3, cout);

end Structural;

• TEST BENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 ENTITY full1_tb IS
END full1_tb;

ARCHITECTURE behavior OF full1_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT fulladd

    PORT(

         x : IN  STD_LOGIC;
         y : IN  STD_LOGIC;
         cin : IN  STD_LOGIC;
         sum : OUT  STD_LOGIC;
         cout : OUT  STD_LOGIC
        );

    END COMPONENT;

   --Inputs
   signal x : STD_LOGIC := '0';
   signal y : STD_LOGIC := '0';
   signal cin : STD_LOGIC := '0';

                --Outputs

   signal sum : STD_LOGIC;
   signal cout : STD_LOGIC;

BEGIN

                -- Instantiate the Unit Under Test (UUT)

   uut: fulladd PORT MAP (

          x => x,
          y => y,
          cin => cin,
          sum => sum,
          cout => cout
        );

   -- Stimulus process

   stim_proc: process

   begin                

               x<='0'; y<='0' ; cin<='0'; wait for 100 ns;
               x<='0'; y<='0' ; cin<='1'; wait for 100 ns;
               x<='0'; y<='1' ; cin<='0'; wait for 100 ns;
               x<='0'; y<='0' ; cin<='1'; wait for 100 ns;         
               x<='1'; y<='0' ; cin<='0'; wait for 100 ns;         
               x<='1'; y<='0' ; cin<='1'; wait for 100 ns;         
               x<='1'; y<='1' ; cin<='0'; wait for 100 ns;
               x<='1'; y<='1' ; cin<='1'; wait for 100 ns;                                         
   end process;
END;

Waveform:

RTL Schematic: